The present invention relates to a method of producing a MOS type power device having an insulation gate such as a power MOSFET and an IGBT, which is capable of preventing the generation of the ON phenomenon, latchup, and the like, of a parasitic bipolar transistor and a parasitic thyristor.
Latchup, which may lead to the breakdown of this kind of semiconductor, and a conventional means for avoiding the phenomenon, will be explained with respect to what is called an IGBT, which is used as an example of a semiconductor.
Referring now to FIG. 2, a sectional view of the main part of a general IGBT, and FIG. 3 an equivalent circuit diagram of the IGBT, when the ON current is applied to the IGBT, the hole current Ip flows from a collector electrode 12 to an n.sup.- drift region 1 passing through a p.sup.+ diffusion region 10 and an n.sup.+ buffer region 2. Ip then passes through a p diffusion region 6 to flow into an emitter electrode 11. During this time, holes pass through a shunting resistance portion 43, which is situated directly under the n.sup.+ emitter region 8 in the p diffusion region 6.
The current Ip, caused by the holes, produces a voltage drop V.sub.F =Ip.times.Rb, wherein Rb represents the resistance of the shunting resistance portion 43. The voltage drop V.sub.F is such that the n+p junction of the n.sup.+ emitter region 8 and the p diffusion region 6 is forwardly biased. The forward bias volta V.sub.A is represented by V.sub.A =.alpha..sub.PNP .multidot.Rb.multidot.Ic, wherein .alpha..sub.PNP represents the gain of a PNP transistor consisting of the p.sup.+ diffusion layer 10, the n.sup.+, n.sup.- diffusion layer (2, 1) and the p diffusion layer 6.
When an NPN transistor consisting of the n.sup.- diffusion layer 1, the p diffusion layer 6 and the n.sup.+ diffusion layer 8 is turned on, and the condition .alpha..sub.PNP +.alpha..sub.NPN =1 is satisfied, the parasitic thyristor assumes latchup, which makes the control of the transistor by a gate signal impossible, and results in the breakdown thereof. This phenomenon is called latchup and the current initiating the latchup is called latchup current.
It is already known that the latchup current is represented by the formula I.sub.L +0.7/.alpha..sub.PNP .multidot.Rb. It is also clear from this formula that if the resistance Rb is reduced, the breakdown of the IGBT is prevented while the current required for latchup to occur increases.
Conventional solutions to the problem of latchup are: introducing a lifetime killer to the n.sup.+ region 1; reducing .alpha..sub.PNP by increasing the impurity density of the n.sup.+ buffer layer 2; and bypassing the hole current by modifying the p.sup.+ diffusion layer 7 shown in FIG. 2 so as to prevent the partial operation of the channel as a p.sup.+ diffusion layer 44 as shown in FIG. 4. All of these methods, however, increase the ON voltage drop of the IGBT.
It is known in the prior art that if the resistance is reduced by shortening the length L.sub.E of the n.sup.+ region portion, directly under which the shunting resistance region 43 is formed, as much as possible, as shown in FIG. 4, the increase in ON voltage drop is prevented. Although the increase in the ON voltage drop is prevented by shortening the length L.sub.E, it is impossible to obtain a sufficiently high latchup current value, since the length L.sub.E of the n.sup.+ emitter region required must be less than 2 to 3 microns, a limitation beyond the accuracy of the photo process.
Accordingly, it is an object of the present invention to provide a method of producing a semiconductor device which is capable of reducing the resistance Rb of the shunting resistance portion 43 as much as possible without increasing the ON voltage drop of the semiconductor device, obtaining a larger latchup current, and greatly improving the turn-off and load short-circuit withstand voltage during the actual use of the semiconductor device.